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International Journals (SCI Impact factor, N/M)

  1. Yung-Chun Wu, Ting-Chang Chang,  Po-Tsun Liu, Chi-Shen Chen, Chun-HaoTu, Hsiao-Wen Zan, Ya-Hsiang Tai, and Chun-Yen Chang,“High-Performance Polycrystalline Silicon Thin-Film Transistor with Multiple Nano-Wire Channels and Lightly-Doped Drain Structure,” Appl. Phys. Lett., (SCI IF = 3.794, 20/128),vol. 84, no. 19,, pp. 3822-3824, 2004.

  2. Yung-Chun Wu, Ting-Chang Chang, Po-Tsun Liu, Yuan-Chun Wu, Cheng-Wei Chou, Chun-HaoTu, Jen-Chung Lou, Chun-Yen Chang,“Mobility Enhancement of Polysilicon Thin-Film Transistor using Nanowire Channels by Pattern- dependent Metal-Induced Lateral Crystallization,”Appl. Phys. Lett., (SCI IF = 3.794, 20/128),87, pp. 143504, 2005.

  3. Yung-Chun Wu, Ting-Chang Chang, Po-Tsun Liu, Chang-Wei Chou, Yuan-Chun Wu, Chun-HaoTu, and Chun-Yen Chang,“Reduction of Leakage Current in Metal-Induced Lateral Crystallization Polysilicon Thin-Film Transistors with Dual-Gate and Multiple Nanowire Channels,”IEEE Electron Device Lett., (SCI IF = 2.789, 26/243), vol. 26, no. 9, pp. 646-648, 2005.

  4. Yung-Chun Wu, Ting-Chang Chang, Po-Tsun Liu, Chi-Shen Chen, Chun-HaoTu, Hsiao-Wen Zan, Ya-Hsiang Tai, Chun-Yen Chang,“Effects of Channel Width on Electrical Characteristics of Polysilicon Thin-Film Transistors with Multiple Nanowire Channels,”IEEETrans. Electron Device, (SCI IF = 2.062, 35/128), vol. 52, no. 10, pp. 2343– 2346, Oct. 2005.

  5. Yung-Chun Wu, Ting-Chang Chang, Po-Tsun Liu, Cheng-Wei Chou, Yuan-Chun Wu, Chun-HaoTu, and Chun-Yen Chang,“High performance Metal-induced Lateral Crystallization Polysilicon Thin-Film         Transistors with Multiple Nano-Wire Channels and Multiple Gates,”IEEE Trans. Nanotechnol.  (IF = 1.800, 45/128), vol. 5, no. 3, pp. 157-162, May,2006.

  6. Yung-Chun Wu, Ting-Chang Chang, Cheng-Wei Chou, Yuan-Chun Wu, Po-Tsun Liu, Chun-HaoTu, Jen-Chung Lou, Chun-Yen Chang,“Effects of Channel Width and NH3 Plasma Passivation on Electrical Characteristics of Polysilicon Thin-Film Transistorsby Pattern-Dependent Metal-Induced Lateral Crystallization,”J. Electrochem. Soc. (SCI IF = 2.588, 1/17), 152, G545-549, 2005.

  7. Shu-Fen Hu, Yung-Chun Wu, Chin-Lung Sung, Chun-Yen Chang, Member, IEEE, and Tiao-Yuan Huang,“A Dual-Gate-Controlled Single-Electron Transistor Using Self-Aligned Polysilicon      Sidewall     Spacer Gates on Silicon-on-Insulator Nanowire,”IEEE Trans. Nanotechnol.(IF = 1.800, 45/128), vol.3, no. 1, pp.93-97, March, 2004.

  8. Shu-Fen Hu, Wei-Zhe Wong, Shiue-Shin Liu, Yung-Chun Wu, Chin-Lung Sung, Tiao-Yuan Huang, and Tzong-JerYang,“A Silicon Nanowire with a Coulomb Blockage Effect at Room Temperature,”Adv. Mater. (SCI IF = 14.829, 3/69) ,vol. 14, no. 10, pp. 736-739, 2002.

  9. Chun-HaoTu, Ting-Chang Chang, Po-Tsun Liu, Hsiao-Wen Zan, Ya-Hsiang Tai, Li-Wei Feng, Yung-Chun Wu, and Chun-Yen Chang,“Improvement of Reliability for Polycrystalline Thin-Film Transistors Using Self-Aligned Fluorinated Silica Glass Spacers,”Electrochem. Solid State Lett.(SCI IF = 2.01, 64/241), 8, G209, 2005.

  10. Chun-HaoTu, Ting-Chang Chang, Po-Tsun Liu, Hsiao-Wen Zan, Ya-Hsiang Tai, Che-Yu Yang, Yung-Chun Wu, Hsin-Chou Liu, Wei-Ren Chen, and Chun-Yen Chang,“Enhanced Performance of Poly-Si Thin Film Transistors Using Fluorine Ions Implantation,”Electrochem. Solid State Lett.(SCI IF = 2.01, 64/241),8, G246, 2005.

  11. Chun-HaoTu, Ting-Chang Chang, Po-Tsun Liu, Chih-Hung Chen, Che-Yu Yang, Yung-Chun Wu, Hsin-Chou Liu, Li-Ting Chang, Chia-Chou Tsai, Simon M. Sze, and Chun-Yen Chang,“Electrical Enhancement of Solid Phase Crystallized Poly-Si Thin-Film Transistors with Fluorine Ion Implantation,”J. Electrochem. Soc. (SCI IF = 2.588, 1/17),Volume 153, Issue 9, pp. G815-G818 2006.

  12. Chun-HaoTu, Ting-Chang Chang, Po-Tsun Liu, Che-Yu Yang, Hsin-Chou Liu, Wei-Ren Chen,   Yung-Chun Wu, Chun-Yen Chang,“Improvement of electrical characteristics for fluorine- ion-implanted poly-Si TFTs using ELC,”IEEE Electron Device Lett., (SCI IF = 2.789, 26/243),vol. 27, no. 4, pp. 262-264, 2006.

  13. Shih-Ching Chen, Ting-Chang Chang, Po-Tsun Liu, Y.C. Wu, C.C. Tsai, T.S. Chang, Chen-HsinLien,“High-performance polycrystalline silicon thin-film transistors with oxide–nitride–oxide gate dielectric and multiple nanowire channels,”Thin Solid Films  (SCI IF =  1.604, 31/68),515 pp. 1112–1116, 2006.

  14. S. C. Chen, T. C. Chang, P. T. Liu, Y. C. Wu, P. H. Yen,  C. F. Weng, Simon M. Sze, C. Y. Chang, C. H. Lien,“Nonvolatile polycrystalline silicon thin-film-transistor memory with oxide/nitride/oxide stack gate dielectrics and nanowire channels,”Appl. Phys. Lett., (SCI IF = 3.794, 20/128),vol. 90, pp. 122111, 2007.

  15. Chun-HaoTu, Ting-Chang Chang, Po-Tsun Liu, Che-Yu Yang, Student Member, IEEE, Li-Wei Feng, Chia-Chou Tsai, Li-Ting Chang, Yung-Chun Wu, Simon M. Sze, Chun-Yen Chang,“Improved Performance of F-Ions-Implanted Poly-Si Thin-Film Transistors Using Solid Phase Crystallization and Excimer Laser Crystallization,”J. Disp. Technol.(SCI IF = 1.663, 49/128),Vol. 3, No. 1, pp. 45-50, 2007.

  16. Yung-Chun Wu*, Ting-Chang Chang, Po-TsunLiu,c and Li-Wei Feng, “Degradation Behaviors of Trigate Nanowires Poly-Si TFTs with NH3 Plasma Passivation under Hot-Carrier Stress”, Electrochem. Solid State Lett.(SCI IF = 2.01, 64/241),10 (8), H235-H238 2007.

  17. Shih-Ching Chen, Ting-Chang Chang, Po-Tsun Liu, Yung-Chun Wu, Po-Shun Lin, Bae-Heng Tseng, Jang-Hung Shy, S. M. Sze, Chun-Yen Chang, and Chen-HsinLien,“A Novel Nanowire Channel Poly-Si TFT Functioning as Transistor and Nonvolatile SONOS Memory,”IEEE Electron Device Lett., (SCI IF = 2.789, 26/243),vol. 28, no. 9, pp. 809-811, 2007.

  18. Shih-Ching Chen, Ting-Chang Chang, Po-Tsun Liu, Yung-Chun Wu, Chin-Cheng Ko, Sidney Yang, Li-Wei Feng,S. M. Sze, Chun-Ten Chang, Chen-HsinLien,“Nonvolatile Si/SiO2 /SiN/SiO2 /Si type polycrystalline silicon thin-film-transistor memory with nanowire channels for improvement of erasing characteristics,”Appl. Phys. Lett., (SCI IF = 3.794, 20/128), 91, p.193103, 2007.

  19. Shih-Ching Chen, Ting-Chang Chang, Po-Tsun Liu, Yung-Chun Wu, Chin-Cheng Ko, Sidney Yang, Li-Wei Feng,S. M. Sze, Chun-Ten Chang, Chen-HsinLien,“Pi-shape gate polycrystalline silicon thin-film transistor for nonvolatile memory applications,”Appl. Phys. Lett., (SCI IF = 3.794, 20/128), 93, p.213101, 2007.

  20. Yung-Chun Wu*, Min-Feng Hung, Chin-Wei Chang, and Po-Wen Su,“Two-bit effect of trigate nanowires polycrystalline silicon thin-film-transistor nonvolatile memory with oxide/nitride/oxide gate dielectrics,”Appl. Phys. Lett., (SCI IF = 3.794, 20/128), 92, 163506, 2008

  21. Yung-ChunWu*, Po-Wen Su, Chin-Wei Chang, and Min-Feng Hung, ,“Novel Twin Poly-Si         Thin-Film Transistors EEPROM With Trigate Nanowire Structure,”IEEE Electron Device Lett., (SCI IF = 2.789, 26/243),vol 29, no.11, pp. 1226-1228, 2008.

  22. Lun-Jyun Chen, Yung-Chun Wu*, Ji-Hong Chiang, Min-Feng Hung, Chin-Wei Chang, and         Po-Wen Su, "Polycrystalline Silicon Thin-Film Flash Memory with Pi-Gate structure and HfO2 charge trapping layer,"Jpn. J. Appl. Phys.(SCI IF =1.067, 82/128),48, pp.120215, 2009.

  23. Lun-Jyun Chen, Yung-Chun Wu*, Tien-Chun Lin, Jyun-Yang Huang,Min-Feng Hung, Jiang-Hung Chen, and Chun-Yen Chang,“Poly-Si Nanowire Nonvolatile Memory withNanocrystal Indium–Gallium–Zinc–OxideCharge-Trapping Layer,”IEEE Electron Device Lett., (SCI IF = 2.789, 26/243),vol31, no.12, pp. 1407-1409, 2010.

  24. Shih-Ching Chen, Ting-Chang Chang, Yung-Chun Wu, Jing-Yi Chin, Yong-EnSyu, S.M. Sze,Chun-Yen Chang, Hsing-Hua Wu, Yi-Chan Chen,“Temperature-dependent memory characteristics of silicon–oxide–nitride–oxide–siliconthin-film-transistors,”Thin Solid Films  (SCI IF =  1.604, 31/68), vol. 518,pp. 3999–4002, 2010.

  25. Lun-Jyun Chen, Yung-Chun Wu*, Ji-Hong Chiang, Min-Feng Hung, Chin-Wei Chang, and Po-Wen Su,“Comprehensive study of Pi-Gate Nanowires Poly-Si TFT Nonvolatile Memory with an HfO2 Charge Trapping Layer,”IEEE Trans. Nanotechnol.  (IF = 1.800, 45/128),vol. 10, No. 2, pp. 260-265, 2011.

  26. Yung-Chun Wu*, Min-Feng Hung, Po-Wen Su,“Improving the performance of nanowires polycrystalline silicon twin thin-film transistors nonvolatile memory by NH3 plasma passivation,”J. Electrochem. Soc. (SCI IF = 2.588, 1/17),vol. 158, issue. 5, pp. H578-H582, 2011.

  27. Min-Feng Hung, Yung-Chun Wu*, and Zih-Yun Tang,“High-performance gate-all-around polycrystalline silicon nanowire with silicon nanocrystals nonvolatile memory,”App. Phys. Lett.(SCI IF = 3.794, 20/128), vol. 98, pp. 162108, 2011.

  28. Hung-Bin Chen, Yung-Chun Wu*, Chao-Kan Yang, Lun-Chun Chen, Ji-Hong Chiang, and Chun-Yen Chang, "Impacts of Poly-Si Nanowire Shape on Gate-All-Around Flash Memory with Hybrid Trap Layer,"IEEE Electron Device Lett., (SCI IF = 2.789, 26/243),vol32, no.10, pp. 11382-1384, 2011.

  29. Jing-Jye Chang, Kuei-Shu Chang-Liao, Tien-Ko Wang, Yung-Chun Wu, Kao-Chao Lin, Chia-Yu Chen, Yu-Mou Chen, Jen-Pei Tseng, Min-Feng Hung,“Electrical Degradation and Recovery of Low-Temperature Polycrystalline Silicon Thin-Film Transistors in Polycrystalline Silicon Plasma Process,”IEEETrans. Electron Device, (SCI IF = 2.062, 35/128), VOL. 58, NO. 8, pp. 2448-2455, 2011.

  30. Min-Feng Hung, Yung-Chun Wu*, Ji-Hong Chiang, Jiang-Hung Chen, Lun-Chun Chen,“Fabrication and Characterization of Twin Poly-Si Thin Film Transistors EEPROM with a Nitride Trapping Layer,”J. Nanosci.Nanotechnol.(SCI IF = 1.171,48/68), in press, 2011.

  31. Hung-Bin Chen, Yung-Chun Wu*, Lun-Chun Chen, Ji-Hong Chiang, Chao-Kan Yang, Chun-Yen Chang,“High Reliability Poly-Si Nanowire Flash Memory with SinanocrystalEmbedded Charge Trapping Layer,”submitted to IEEE Electron Device Lett., (SCI IF = 2.789, 26/243),2011.

  32. Min-Feng Hung,Yung-Chun Wu*, Tsung-Ming Tsai, Jiang-Hung Chen, and Yi-Ray Jhan,“Enhancement of Two-Bit Performance of Dual-Pi-Gate Charge Trapping Layer Flash Memory,”submitted to Appl. Phys. Express (SCI IF = 2.731, 23/128),vol.5, p.p. 121801,2012.

  33. Min-Feng Hung, Yung-Chun Wu*, and Jiang-Hung Chen,“2-bit operation based on modulated Fowler-Nordheim tunneling in chargetrappingflash memory cell,”App. Phys. Lett.(SCI IF = 3.794, 20/128), vol. 100, p.p. 052107, 2012.

  34. Hung-Bin Chen, Yung-Chun Wu*, Lun-Chun Chen, Ji-Hong Chiang,Chao-Kan Yang, and Chun-Yen Chang,“High-Reliability Trigate Poly-Si Channel FlashMemory Cell With Si-Nanocrystal EmbeddedCharge-Trapping Layer,”IEEE Electron Device Lett., (SCI IF = 2.789, 26/243),vol.33,no.4, p.p. 537-539, 2012.

  35. Hsin-Hui Hu, Yong-Ren Jheng, Yung-Chun Wu*, Min-Feng Hung, and Guo-Wei Huang,“Low-Frequency Noise in SONOS-TFT withTrigateanowire Structure Under Program/Erase Operation,”IEEE Electron Device Lett., (SCI IF = 2.789, 26/243),vol.33, no.9, p.p.1276-1278, 2012.

  36. Min-Feng Hung, Yung-Chun Wu*, Shun-Cheng Tien, and Jiang-Hung Chen,“Polycrystalline-Si TFT TANOS Flash Memory Cell with Si Nanocrystals for high Program/Erase Speed and Good Retention,”IEEE Electron Device Lett., (SCI IF = 2.789, 26/243),vol.33, no.5, p.p.649-651, 2012.

  37. Yu-Hsien Lin*, Yung-Chun Wu, Min-Feng Hung, Jiang-Hung Chen,“Charge Storage Characteristics of Pi-Gate Poly-Si Nanowires TaN-Al2O3-Si3N4-SiO2-Si Flash Memory,”J. Electrochem. Soc. (SCI IF = 3.729, 0/0),no.7 pp. 8648-8658, 2012.

  38. Yu-Hsien Lin*, Yung-Chun Wu, Bo-Yu Lai,“Collection Efficiency Enhancement of Injected Electrons in Dye-sensitized Solar Cells with a Ti Interfacial Layer and TiCl4 Treatment,”J. Electrochem. Soc. (SCI IF = 3.729, 0/0), no.7 pp. 9478-9487, 2012.

  39. Tzong-Han Tsai, Yung-Chun Wu*, Shih-Sian Yang, and Chun-Hao Chen,“Optimization of Amorphous Si/Crystalline Si Heterojunction Solar Cells by BF2 Ion Implantation,”Jpn. J. Appl. Phys.(SCI IF =1.067, 82/128),vol.51, p.p. 04DP07, 2012.

  40. Ya-Chi Cheng, Yung-Chun Wu*, Hung-Bin Chen, Ming-Hung Han, Nan-Heng Lu,“High voltage characteristics of junctionless poly-silicon thin film transistors,”App. Phys. Lett.(SCI IF = 3.794, 20/128), vol. 103. pp.123510, 2013.

  41. Yi-Ruei Jhan, Yung-Chun Wu*, Hsin-Yi Lin, and Min-Feng Hung,“Pi-gate tunneling field-effect transistor charge trapping nonvolatile memory based on all tunneling transportation,” App. Phys. Lett.(SCI IF = 3.794,20/128), vol. 103. pp.053118, 2013

  42. Ming-Hung Han, Chun-Yen Chang, Hung-Bin Chen, Ya-Chi Cheng,and Yung-Chun Wu*,“Device and Circuit Performance Estimation of Junctionless Bulk FinFETs,”IEEETrans. Electron Device, (SCI IF = 2.062, 35/128),vol.60, no.6, p.p. 1807-1812, 2013.

  43. Ming-Hung Han, Chun-Yen Chang, Yi-RueiJhan, Jia-Jiun Wu,Hung-Bin Chen, Ya-Chi Cheng, and Yung-Chun Wu*,“Characteristic of p-Type Junctionless Gate-All-Around Nanowire Transistor and Sensitivity Analysis, ”IEEE Electron Device Lett., (SCI IF = 2.789, 26/243),vol.34, no.2, p.p. 157-159, 2013.

  44. Hung-Bin Chen, Chun-Yen Chang, Nan-Heng Lu, Jia-Jiun Wu, Ming-Hung Han,Ya-Chi Cheng, and Yung-Chun Wu*,“Characteristics of Gate-All-Around Junctionless Poly-Si TFTs With an Ultrathin Channel,”IEEE Electron Device Lett., (SCI IF = 2.789, 26/243),vol.34, no.7, p.p. 897-899, 2013.

  45. Ming-Hung Han, Chun-Yen Chang, Hung-Bin Chen,Jia-Jiun Wu, Ya-Chi Cheng, and Yung-Chun Wu*,“Performance Comparison Between Bulkand SOI Junctionless Transistors,”IEEE Electron Device Lett., (SCI IF = 2.789, 26/243),vol.34, no.2, p.p. 169-171, 2013.

  46. Min-Feng Hung, Yung-Chun Wu*, Jiun-Jye Chang, and Kuei-Shu Chang-Liao,“Twin Thin-Film Transistor Nonvolatile Memory Withan Indium–Gallium–Zinc–Oxide Floating Gate,”IEEE Electron Device Lett., (SCI IF = 2.789, 26/243),vol.34, no.1, p.p. 75-77, 2013.

  47. Hung-Bin Chen, Chun-Yen Chang, Min-Feng Hung, Zih-Yun Tang, Ya-Chi Cheng, and Yung-Chun Wu*,“A 2-bit/Cell Gate-All-Around Flash Memory of Self-Assembled Silicon Nanocrystals,”Jpn. J. Appl. Phys.(SCI IF =1.067, 82/128),vol.52, p.p. 021302, 2013.

  48. Mu-Shih Yeh, Yung-Chun Wu*, Min-Feng Hung, Kuan-Cheng Liu, Yi-RueiJhan, Lun-Chun Chenand Chun-Yen Chang,“Fabrication, characterization and simulation ofΩ-gate twin poly-Si FinFET nonvolatile memory,”Nanoscale Res. Lett.(SCI IF=2.524, 26/128),vol. 8, no.331, p.p. 1-5, 2013.

  49. Mu-Shih Yeh, Yao-Jen Lee, Min-Feng Hung, Kuan-Cheng Liu, and Yung-Chun Wu*,“High-Performance Gate-All-Around Poly-Si Thin-Film Transistors by Microwave AnnealingWith NH3 Plasma Passivation,”IEEE Trans. Nanotechnol.(IF = 1.800, 45/128), vol.12, no.4, p.p. 636-639, Jul., 2013.

  50. Mu-Shih Yeh, Yung-Chun Wu*,Ming-Hsien Chung, Yi-RueiJhan, Kuei-Shu Chang-Liao,

  51. Kuan-Cheng Liu, Min-Hsin Wu, and Min-Feng Hung, “Investigation of p-channel and n-channel junctionless gate-all-around polycrystalline silicon nanowires with silicon nanocrystals nonvolatile memory,”Applied Physics Letters (SCI IF =3.794, 20/128),vol. 105, 042109 2014.

  52. Jhen-Yu Tsai, Hsin-Hui Hu, Yung-Chun Wu*, Yi-Rue Jhan, Kun-Ming Chen, and Guo-Wei Huang, “A Novel Hybrid Poly-Si NanowireLDMOS With Extended Drift,”IEEE Electron Device Let(SCI IF =2.789, 26/243)t.,Vol. 35, no. 3, 2014.

  53. Yi-Ruei Jhan, Yung-Chun Wu*, Member, IEEE, Hsin-Yi Lin, Min-Feng Hung, Yu-Hsiang Chen, and Mu-Shih Yeh, “High Performance of Fin-Shaped Tunnel Field-EffectTransistor SONOS Nonvolatile Memory With All Programming Mechanisms in Single Device,”IEEE Trans. Electron Device, (SCI IF = 2.062, 35/128),Vol. 61, no. 7, 2014

  54. Ya-Chi Cheng , Hung-Bin Chen , Ming-Hung Han , Nan-Heng Lu , Jun-Ji Su ,Chi-Shen Shao and Yung-Chun Wu*,“Temperature dependence of electronic behaviors in quantum dimension junctionless thin-film transistor,” Nanoscale Research Letters ,2014.

  55. Ya-Chi Cheng, Hung-Bin Chen, Jun-Ji Su1, Chi-Shen Shao, Cheng-Ping Wang, Chun-Yen Chang and Yung-Chun Wu*,“Characterizing the electrical properties of raised S/D junctionless thin-film transistors with a dual-gate structure” Nanoscale Research Letters ,2014.

  56. Mu-Shih Yeh, Yung-Chun Wu*, Min-Hsin Wu, Ming-Hsien Chung, Yi-RueiJhan, and Min-Feng Hung,“Characterizing the  Electrical Properties of a Novel Junctionless Poly-Si Ultrathin-Body Field-Effect Transistor Using a Trench Structure,” IEEE Electron Device Lett., (SCI IF = 3.023, 29/248), vol. 36, no. 2,2015.

  57. Ya-Chi Cheng, Hung-Bin Chen, Jun-Ji Su, Chi-Shen Shao, VasanthanThirunavukkarasu, Chun-Yen Chang, and Yung-Chun Wu* ,“Characteristics of a Novel Poly-Si P-Channel Junctionless Thin-Film Transistor With Hybrid P/N-Substrate,” IEEE Electron Device Lett., (SCI IF = 3.023, 29/248), vol. 36, no. 2,2015.

  58. Yi-Ruei Jhan, Yung-Chun Wu*,Yu-Long Wang, Yao-Jen Lee, Min-Feng Hung, Hsin-Yi Lin, Yu-Hsiang Chen, and Mu-Shih Yeh, “Low-Temperature Microwave Annealing for Tunnel Field-Effect Transistor,” IEEE Electron Device Lett., (SCI IF = 3.023, 29/248), vol. 36, no. 2,2015.

  59. Ya-Chi Cheng, Hung-Bin Chen, Chun-Yen Chang, Yi-Kang Wu, Yi-Jia Shih, Chi-Shen Shao, and Yung-Chun Wu*,“Back-gate bias effect on nanosheet hybrid P/N channel of junctionless thin-film transistor with increased Ion versus decreased Ioff,” Applied Physics Letters ,107, 182105 (2015).

  60. Yi-Ruei Jhan, Vasanthan Thirunavukkarasu, Cheng-Ping Wang, and Yung-Chun Wu*, “Performance Evaluation of Silicon and Germanium Ultrathin Body (1 nm) Junctionless Field-Effect Transistor With Ultra short Gate Length (1 nm and 3 nm),” IEEE Electron Device Lett., vol. 36, no. 7, 2015.

  61. Vasanthan Thirunavukkarasu, Yi-Ruei Jhan, Yan-Bo Liu, and Yung-Chun Wu*,“Performance of Inversion, Accumulation, and Junctionless Mode n-Type and p-Type Bulk Silicon FinFETs With 3-nm Gate Length.” IEEE Electron Device Lett., vol. 36, no. 7, 2015.

  62. Ya-Chi Cheng, Hung-Bin Chen, Jun-Ji Su, Chi-Shen Shao, Vasanthan Thirunavukkarasu, Chun-Yen Chang, and Yung-Chun Wu*,“Characteristics of a Novel Poly-Si P-Channel Junctionless Thin-Film Transistor With Hybrid P/N-Substrate,” IEEE Electron Device Lett., vol. 36, no. 2, 2015.

  63. Yu-Hsien Lin, Mu-Shih Yeh, Yi-Ruei Jhan, Ming-Hsien Chung, Chien-Chih Chung, Min Yen, and Yung-Chun Wu*, Band-to-Band Hot Hole Erase Mechanism of p-Channel Junctionless Silicon Nanowire Nonvolatile Memory, IEEE Trans. Nanotechnol Vol. 15, no: 1, Jan. 2016.

  64. Yu-Ru Lin, Wei-Cheng Wang, Lun-Chun Chen, and Yung-Chun Wu*,“Artificial Defects in Si3N4 Enhance Nonvolatile Memory Performance of Ultra-Thin Body Poly-Si Junctionless Field-Effect Transistors” ECS Journal of Solid State Science and Technology, vol.5,no. 4 ,2016.

  65. Lun-Chun Chen , Mu-Shih Yeh, Ko-Wei Lin, Min-Hsin Wu, and Yung-Chun Wu*,“Junctionless Poly-Si Nanowire FET With Gated Raised S/D,” Journal of the electron device society, 2016.

  66. Vasanthan Thirunavukkarasu, Yi-Ruei Jhan, Yan-Bo Liu, Erry Dwi Kurniawan, Yu Ru Lin, Shang-Yi Yang, Che-Hsiang Cheng, and Yung-Chun Wu*,“Gate-all-around junctionless silicon transistors with atomically thin nanosheet channel (0.65 nm) and record sub-threshold slope (43 mV/dec),” Applied Physics Letters ,110, 032101 (2017).

  67. Lun-Chun Chen, Mu-Shih Yeh, Yu-Ru Lin, Ko-Wei Lin, Min-Hsin Wu, Vasanthan Thirunavukkarasu, and Yung-Chun Wu*,“The physical analysis on electrical junction of junctionless FET,” AIP Advances, 7, 025301 (2017).

  68. Lun-Chun Chen , Yu-Ru Lin,Yu-Shuo Chang, and Yung-Chun Wu*, “High-Performance Stacked Double-LayerN-channel Poly-Si Nanosheet Multigate Thin-Film Transistors,” IEEE Electron Device Lett., ( Volume: 38 , Issue: 9 , Sept. 2017.

  69. Erry Dwi Kurniawan,  Hao Yang Chia-Chou Lin, Yung-Chun Wu* , “Effect of fin shape of tapered FinFETs on the device performance in 5-nm node CMOS technology”,  Microelectronics Reliability, vol. 78, 2018.

  70. Vasanthan Thirunavukkarasu, Jaehyun Lee c, Toufik Sadi, Vihar P. Georgiev, Fikru-Adamu Lema, Karuppasamy Pandian Soundarapandian, Yi-Ruei Jhan, Shang-Yi Yang, Yu-Ru Lin, Erry Dwi Kurniawan, Yung-Chun Wu*, Asen Asenov, “Investigation of inversion, accumulation and junctionless mode bulk Germanium FinFETs” Superlattices and Microstructures, vol. 108, 2017.

  71. Erry Dwi Kurniawan, Shang-Yi Yang, Vasanthan Thirunavukkarasu, and Yung-Chun Wu*, “Analysis of Ge-Si Heterojunction Nanowire Tunnel FET: Impact of Tunneling Window of Band-to-Band Tunneling Model”, ECS Journal of The Electrochemical Society, 164 (11) E3354-E3358 (2017) .

  72. Yu-Ru Lin, Wan-Ting Tsai, Yung-Chun Wu and Yu-Hsien Lin, "Ultra Thin Poly-Si Nanosheet     Junctionless Field-Effect Transistor with Nickel Silicide Contact", Materials, 2017, 10, 1276; doi:10.3390/ma10111276

  73. Yu-Ru Lin, Yi-Wei Chiang, Yu-Hsien Lin , Wei-Cheng Wang, and Yung-Chun Wu* “Comparison With Nitride Interface Defects and Nanocrystals for Charge Trapping Layer Nanowire Gate-All-Around Nonvolatile Memory Performance” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 65, NO. 2, FEBRUARY pp. 493-498, 2018

  74. Lun-Chun Chen, Hung-Bin Chen, Yu-Shuo Chang, Shih-Han Lin, Ming-Hung Han, Jia-Jiun Wu, Mu-Shih Yeh, Yu-Ru Lin, and Yung-Chun Wu* “Low-Voltage Programmable Gate-All-Around (GAA) Nanosheet TFT Nonvolatile Memory Using Band-to-Band Tunneling Induced Hot Electron (BBHE) Method”, IEEE Journal of the Electron Devices Society, 2019

  75. Meng-Ju Tsai, Pin-Jui Chen, Chieng-Chung Hsu, Dun-Bao Ruan , Fu-Ju Hou, Po-Yang Peng, and Yung-Chun Wu* “ Atomic-Level Analysis of Sub-5-nm-Thick Hf0.5Zr0.5O2 and Characterization of Nearly Hysteresis-Free Ferroelectric FinFET, ” IEEE Electron Devic Lett., vol. 40, No. 8, 2019.

  76. Meng-Ju Tsai, Pin-Jui Chen, Dun-Bao Ruan, Fu-Ju Hou, Po-Yang Peng, Liu-Gu Chen, and Yung-Chun Wu*“Investigation of 5-nm-Thick Hf0.5Zr0.5O2 Ferroelectric FinFET Dimensions for Sub-60-mV/Decade Subthreshold Slope, ” IEEE Journal of the Electron Devices Society, Vol. 7, 2019.

  77. Chong-Jhe Sun, Meng-Ju Tsai, Siao-Cheng Yan, Tzu-Ming Chu, Chieng-Chung Hsu, Chun-Lin Chu, GuanG-Li Luo, and Yung-Chun Wu* “        Low Ge Content Ultra-Thin Fin Width (5nm) Monocrystalline SiGe n-Type FinFET With Low Off State Leakage and High ION/IOFF Ratio,” IEEE Journal of the Electron Devices Society, vol. 8, pp. 1016 – 1020, 2020.

  78. Siao-Cheng Yan, Chong-Jhe Sun, Meng-Ju Tsai, Lun-Chun Chen, Mu-Shih Yeh, Chien-Chang Li, Yao-Jen Lee, and Yung-Chun Wu* “Germanium Twin-Transistor Nonvolatile Memory With FinFET Structure,” IEEE Journal of the Electron Devices Society, vol. 8, pp. 589 – 593, 2020.

  79. Yi-Wen Lin, Chong-Jhe Sun, Hao-Hsiang Chang, Yu-Hsien Huang, Tung-Yuan Yu, Yung-Chun Wu, and Fu-Ju Hou “Self-induced ferroelectric 2-nm-thick Ge doped HfO2 thin film applied to Ge nanowire ferroelectric gate-all-around field-effect transistor,” Applied Physics Letters, 117, 262109, 2020.

  80. Y.-W. Lin, T.-Y. Yu, C.-J. Su, Y.-N. Chen, H.-H. Chang, G.-L. Luo, C.-T. Wu, W.-F. Wu, K.-L. Lin, F.-J. Hou,*, Y.-C. Wu, and W.-K. Yeh, "Sub-60 mV/dec Germanium Nanowire Field-Effect Transistors with 2-nm-thick Ferroelectric Hf0.5Zr0.5O2," 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2021, pp. 1-2, doi: 10.1109/VLSI-TSA51926.2021.9440120.

  81. Siao-Cheng Yan , Guan-Min Lan, Chong-Jhe Sun, Ya-Han Chen, Chen-Han Wu, Hao-Kai Peng, Yu-Hsien Lin , Yung-Hsien Wu , and Yung-Chun Wu, "High Speed and Large Memory Window Ferroelectric HfZrO₂ FinFET for High-Density Nonvolatile Memory," in IEEE Electron Device Letters, vol. 42, no. 9, pp. 1307-1310, Sept. 2021, doi: 10.1109/LED.2021.3097777.

  82. Sun, Chong-Jhe, Chen-Han Wu, Yi-Ju Yao, Shan-Wen Lin, Siao-Cheng Yan, Yi-Wen Lin, and Yung-Chun Wu. 2022. "Threshold Voltage Adjustment by Varying Ge Content in SiGe p-Channel for Single Metal Shared Gate Complementary FET (CFET)" Nanomaterials 12, no. 20: 3712. https://doi.org/10.3390/nano12203712

  83. Yan, Siao-Cheng, Chen-Han Wu, Chong-Jhe Sun, Yi-Wen Lin, Yi-Ju Yao, and Yung-Chun Wu. 2022. "Trench FinFET Nanostructure with Advanced Ferroelectric Nanomaterial HfZrO2 for Sub-60-mV/Decade Subthreshold Slope for Low Power Application" Nanomaterials 12, no. 13: 2165. https://doi.org/10.3390/nano12132165

  84. ​Yan, Siao-Cheng, Wu, Chen-Han, Sun, Chong-Jhe; Zhong, Xin-Chan; Chang, Chih-Siang; Peng, Hao-Kai; Wu, Yung-Hsien; Wu, Yung-Chun "Multilevel Cell Ferroelectric HfZrO FinFET With High Speed and Large Memory Window Using AlON Interfacial Layer" IEEE Electron Device Letters, vol. 44, no. 1, pp. 44-47, Jan. 2023.

  85. Sun, Chong-Jhe; Yao, Yi-Ju; Yan, Siao-Cheng; Lin, Yi-Wen; Lin, Shan-Wen; Hou, Fu-Ju; Luo, Guang-Li; Wu, Yung-Chun; "Investigation of SiGe/Si Bilayer Inverted-T Channel Gate-All-Around Field-Effect-Transistor With Self-Induced Ferroelectric Ge Doped HfO₂"IEEE Journal of the Electron Devices Society, vol. 10, pp. 408-412, 2022.

  86. Yao, Yi-Ju; Tseng, Ting-Yu; Yang, Ching-Ru; Lin, Tsai-Jung; Chang, Heng-Jia; Luo, Guang-Li; Hou, Fu-Ju; Chang-Liao, Kuei-Shu; Wu, Yung-Chun; "SiGe/Si Superlattice Ferroelectric HfZrO 2 ΩFET and CMOS Inverter with SS min, n= 62.4 mV/dec, I ON/I OFF> 1.0× 10 7, and Voltage Gain= 111.4 V/V"IEEE Electron Device Letters, vol. 45, no. 2, pp. 260-263, Feb. 2024

  87. Lin, Yi-Wen; Lin, Shan-Wen; Chen, Bo-An; Sun, Chong-Jhe; Yan, Siao-Cheng; Luo, Guang-Li; Wu, Yung-Chun; Hou, Fu-Ju; "3-D Self-Aligned Stacked Ge Nanowire pGAAFET on Si nFinFET of Single Gate CFET"IEEE Journal of the Electron Devices Society, vol. 11, pp. 480-484, 2023

  88. Yao, Y.-J.; Yang, C.-R.; Tseng, T.-Y.; Chang, H.-J.; Lin, T.-J.; Luo, G.-L.; Hou, F.-J.; Wu, Y.-C.; Chang-Liao, K.-S. High-Performance P- and N-Type SiGe/Si Strained Super-Lattice FinFET and CMOS Inverter: Comparison of Si and SiGe FinFET. Nanomaterials 2023.

  89. Wei, Chen-You; Huang, Ming-Yueh; Yan, Siao-Cheng; Wu, Yung-Chun;  "High-Speed and Low-Power Ferroelectric HfO₂/ZrO₂ Superlattice FinFET Memory Device Using AlON Interfacial Layer," in IEEE Transactions on Electron Devices, vol. 71, no. 6, pp. 3977-3980, June 2024.

  90. Yao, Yi-Ju; Lin, Tsai-Jung; Wei, Chen-You; Chen, Bo-Xu; Fang, Yung-Teng; Chang, Heng-Jia; Fu, Yu-Min; Luo, Guang-Li; Hou, Fu-Ju; Wu, Yung-Chun;  "High-Temperature Retention Stability of Multibit Ferroelectric HfZrO₂ FinFET With SiGe/Si Superlattice Channel for Enhanced Speed and Memory Window," in IEEE Transactions on Electron Devices, vol. 71, no. 10, pp. 5975-5979, Oct. 2024.

  91. Lin, Yi-Wen; Chen, Bo-An; Huang, Kai-Wei; Chen, Bo-Xu; Luo, Guang-Li; Wu, Yung-Chun; Hou, Fu-Ju; "3-D Self-Aligned Stacked Ge Nanowires Complementary FET Featuring Single Gate Simple Process," in IEEE Electron Device Letters, vol. 45, no. 10, pp. 2013-2016, Oct. 2024.

  92. Lin, Yi-Wen; Huang, Yu-Hsien; Lin, Shan-Wen; Luo, Guang-Li; Lin, Yu-Hsien; Wu, Yung-Chun; Hou, Fu-Ju; "Self-Induced Ge-Doped HfO2 Applied to Ge Stacked Nanowires Ferroelectric Gate-All-Around Field-Effect Transistor with Steep Subthreshold Slope Under O3 Treatment with GeO2 as Interfacial Layer", ECS Journal of Solid State Science and Technology, 2024.

  93. Chen-You Wei; Yung-Teng Fang; Yi-Ju Yao; Chih-Chao Yang; Fu-Ju Hou; Chien-Chun Chen, "High-Reliability HfO2/ZrO2 Superlattice Ferroelectric Poly-Si FinFET Memory Device Utilizing Green Laser Crystallization," in IEEE Electron Device Letters, 2024.

國際期刊論文 International Journals (2016-2024)

  1. Yu-Ru Lin, Wei-Cheng Wang, Lun-Chun Chen, and Yung-Chun Wu*,“Artificial Defects in Si3N4 Enhance Nonvolatile Memory Performance of Ultra-Thin Body Poly-Si Junctionless Field-Effect Transistors” ECS Journal of Solid State Science and Technology,vol.5,no. 4 ,2016.

  2. Lun-Chun Chen , Mu-Shih Yeh, Ko-Wei Lin, Min-Hsin Wu, and Yung-Chun Wu*,“Junctionless Poly-Si Nanowire FET With Gated Raised S/D,” Journal of the electron device society, 2016.

  3. Vasanthan Thirunavukkarasu, Yi-Ruei Jhan, Yan-Bo Liu, Erry Dwi Kurniawan, Yu Ru Lin, Shang-Yi Yang, Che-Hsiang Cheng, and Yung-Chun Wu*,“Gate-all-around junctionless silicon transistors with atomically thin nanosheet channel (0.65 nm) and record sub-threshold slope (43 mV/dec),” Applied Physics Letters ,110, 032101 (2017).

  4. Lun-Chun Chen, Mu-Shih Yeh, Yu-Ru Lin, Ko-Wei Lin, Min-Hsin Wu, Vasanthan Thirunavukkarasu, and Yung-Chun Wu*,“The physical analysis on electrical junction of junctionless FET,” AIP Advances, 7, 025301 (2017).

  5. Lun-Chun Chen , Yu-Ru Lin,Yu-Shuo Chang, and Yung-Chun Wu,“High-Performance Stacked Double-LayerN-channel Poly-Si Nanosheet Multigate Thin-Film Transistors,” IEEE Electron Device Lett., vol.PP, no.99, pp.1-1(2017).

  6. Erry Dwi Kurniawan,  Hao Yang Chia-Chou Lin, Yung-Chun Wu , “Effect of fin shape of tapered FinFETs on the device performance in 5-nm node CMOS technology”,  Microelectronics Reliability, vol. 78, 2017.

  7. Vasanthan Thirunavukkarasu, Jaehyun Lee c, Toufik Sadi, Vihar P. Georgiev, Fikru-Adamu Lema, Karuppasamy Pandian Soundarapandian, Yi-Ruei Jhan, Shang-Yi Yang, Yu-Ru Lin, Erry Dwi Kurniawan, Yung-Chun Wu, Asen Asenov, “Investigation of inversion, accumulation and junctionless mode bulk Germanium FinFETs” Superlattices and Microstructures, vol. 108, 2017.

  8. Erry Dwi Kurniawan, Shang-Yi Yang, Vasanthan Thirunavukkarasu, and Yung-Chun Wu*, “Analysis of Ge-Si Heterojunction Nanowire Tunnel FET: Impact of Tunneling Window of Band-to-Band Tunneling Model”, ECS Journal of The Electrochemical Society, 164 (11) E3354-E3358 (2017) .

  9. Yu-Ru Lin, Wan-Ting Tsai, Yung-Chun Wu* and Yu-Hsien Lin, "Ultra Thin Poly-Si Nanosheet Junctionless Field-Effect TransistorwithNickel Silicide Contact", Materials, 2017, 10, 1276; doi:10.3390/ma10111276

  10. Yu-Ru Lin, Yi-Wei Chiang, Yu-Hsien Lin , Wei-Cheng Wang, and Yung-Chun Wu* “Comparison With Nitride Interface Defects and Nanocrystals for Charge Trapping Layer Nanowire Gate-All-Around Nonvolatile Memory Performance” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 65, NO. 2, FEBRUARY pp. 493-498, 2018

  11. Lun-Chun Chen, Hung-Bin Chen, Yu-Shuo Chang, Shih-Han Lin, Ming-Hung Han, Jia-Jiun Wu, Mu-Shih Yeh, Yu-Ru Lin, and Yung-Chun Wu* “Low-Voltage Programmable Gate-All-Around (GAA) Nanosheet TFT Nonvolatile Memory Using Band-to-Band Tunneling Induced Hot Electron (BBHE) Method”, IEEE Journal of the Electron Devices Society, 2019

  12. Meng-Ju Tsai, Pin-Jui Chen, Chieng-Chung Hsu, Dun-Bao Ruan , Fu-Ju Hou, Po-Yang Peng, and Yung-Chun Wu* “ Atomic-Level Analysis of Sub-5-nm-Thick Hf0.5Zr0.5O2 and Characterization of Nearly Hysteresis-Free Ferroelectric FinFET, ” IEEE Electron Devic Lett., vol. 40, No. 8, 2019.

  13. Meng-Ju Tsai, Pin-Jui Chen, Dun-Bao Ruan, Fu-Ju Hou, Po-Yang Peng, Liu-Gu Chen, and Yung-Chun Wu* “Investigation of 5-nm-Thick Hf0.5Zr0.5O2 Ferroelectric FinFET Dimensions for Sub-60-mV/Decade Subthreshold Slope, ” IEEE Journal of the Electron Devices Society, Vol. 7, 2019.

  14. Meng-Ju Tsai, Kang-Hui Peng, Chong-Jhe Sun, Siao-Cheng Yan, Hieng-Chung Hsu, Yu-Ru Lin, Yu-Hsien Lin , and Yung-Chun Wu *"Fabrication and Characterization of Stacked Poly-Si Nanosheet With Gate-All-Around and Multi-Gate Junctionless Field Effect Transistors," in IEEE Journal of the Electron Devices Society, vol. 7, pp. 1133-1139, 2019.

  15. Yu-Ru Lin, Yu-Hsien Lin , Yu-Fang Chen, Ya-Ting Hsu, Ya-Han Chen, Yu-Hsien Huang , and Yung-Chun Wu, “Performance of Junctionless and Inversion-Mode Thin-Film Transistors With Stacked Nanosheet Channels “IEEE TRANSACTIONS ON NANOTECHNOLOGY, Volume 19, 2020.

  16. SIAO-CHENG YAN, CHONG-JHE SUN, MENG-JU TSAI, LUN-CHUN CHEN, MU-SHIH YEH, CHIEN-CHANG LI, YAO-JEN LEE, AND YUNG-CHUN WU* “Germanium Twin-Transistor Nonvolatile Memory With FinFET Structure, IEEE Journal of the Electron Devices Society, Vol. 8, 2020.

  17. CHONG-JHE SUN, MENG-JU TSAI, SIAO-CHENG YAN1, TZU-MING CHU1, CHIENG-CHUNG HSU, CHUN-LIN CHU, GUANG-LI LUO, AND YUNG-CHUN WU*, Low Ge Content Ultra-Thin Fin Width (5nm) Monocrystalline SiGe n-Type FinFET With Low Off State Leakage and High ION/IOFF Ratio, IEEE Journal of the Electron Devices Society, Vol. 8, 2020.

  18. Yi-Wen Lin, Chong-Jhe Sun, Hao-Hsiang Chang, Yu-Hsien Huang, Tung-Yuan Yu, Yung-Chun Wu, and Fu-Ju Hou, “Self-induced ferroelectric 2-nm-thick Ge-doped HfO 2 thin film applied to Ge nanowire ferroelectric gate-all-around field-effect transistor”, Appl. Phys. Lett. 117, 262109, 2020.

  19. Siao-Cheng Yan , Guan-Min Lan, Chong-Jhe Sun, Ya-Han Chen, Chen-Han Wu , Hao-Kai Peng,　Yu-Hsien Lin , Yung-Hsien Wu , and Yung-Chun Wu, "High Speed and Large Memory Window Ferroelectric HfZrO₂ FinFET for High-Density Nonvolatile Memory," in IEEE Electron Device Letters, vol. 42, no. 9, pp. 1307-1310, Sept. 2021, doi: 10.1109/LED.2021.3097777.

  20. Siao-Cheng Yan, Chen-Han Wu, Chong-Jhe Sun, Yi-Wen Lin, Yi-Ju Yao, and Yung-Chun Wu*, “Trench FinFET Nanostructure with Advanced Ferroelectric Nanomaterial HfZrO2 for Sub-60-mV/Decade Subthreshold Slope for Low Power Application”, Nanomaterials, 12(13), pp. 2165, June 2022.

  21. Chong-Jhe Sun, Chen-Han Wu, Yi-Ju Yao, Shan-Wen Lin, Siao-Cheng Yan, Yi-Wen Lin and Yung-Chun Wu*, “Threshold Voltage Adjustment by Varying Ge Content in SiGe p-Channel for Single Metal Shared Gate Complementary FET (CFET)”, Nanomaterials, 12(20), pp. 3712, Oct. 2022.

  22. Siao-Cheng Yan, Chen-Han Wu, Chong-Jhe Sun, Xin-Chan Zhong, Chih-Siang Chang, Hao-Kai Peng, Yung-Hsien Wu, and Yung-Chun Wu*, “Multilevel Cell Ferroelectric HfZrO2 FinFET with High Speed and Large Memory Window using AlON Interfacial Layer”, IEEE Electron Device Letters, vol. 44, no. 1, January 2023. IEEE EDL Cover page

  23. Yi-Ju Yao, Ching-Ru Yang, Ting-Yu Tseng, Heng-Jia Chang, Tsai-Jung Lin, Guang-Li Luo, Fu-Ju Hou, Yung-Chun Wu*, and Kuei-Shu Chang-Liao*, “High-Performance P- and N-Type SiGe/Si Strained Super-Lattice FinFET and CMOS Inverter: Comparison of Si and SiGe FinFET”, Nanomaterials, 13(8), pp. 1310, April 2023.

  24. Yi-Wen Lin, Shan-Wen Lin, Bo-An Chen, Chong-Jhe Sun, Siao-Cheng Yan, Guang-Li Luo, Yung-Chun Wu*, Fu-Ju Hou*, “3-D Self-Aligned Stacked Ge Nanowire pGAAFET on Si nFinFET of Single Gate CFET”, IEEE Journal of the Electron Devices Society, vol. 11, pp. 480-484, Aug. 2023.

  25. Yao, Y.-J.; Yang, C.-R.; Tseng, T.-Y.; Chang, H.-J.; Lin, T.-J.; Luo, G.-L.; Hou, F.-J.; Wu, Y.-C.; Chang-Liao, K.-S. High-Performance P- and N-Type SiGe/Si Strained Super-Lattice FinFET and CMOS Inverter: Comparison of Si and SiGe FinFET. Nanomaterials 2023.

  26. Wei, Chen-You; Huang, Ming-Yueh; Yan, Siao-Cheng; Wu, Yung-Chun;  "High-Speed and Low-Power Ferroelectric HfO₂/ZrO₂ Superlattice FinFET Memory Device Using AlON Interfacial Layer," in IEEE Transactions on Electron Devices, vol. 71, no. 6, pp. 3977-3980, June 2024.

  27. Yao, Yi-Ju; Lin, Tsai-Jung; Wei, Chen-You; Chen, Bo-Xu; Fang, Yung-Teng; Chang, Heng-Jia; Fu, Yu-Min; Luo, Guang-Li; Hou, Fu-Ju; Wu, Yung-Chun;  "High-Temperature Retention Stability of Multibit Ferroelectric HfZrO₂ FinFET With SiGe/Si Superlattice Channel for Enhanced Speed and Memory Window," in IEEE Transactions on Electron Devices, vol. 71, no. 10, pp. 5975-5979, Oct. 2024.

  28. Lin, Yi-Wen; Chen, Bo-An; Huang, Kai-Wei; Chen, Bo-Xu; Luo, Guang-Li; Wu, Yung-Chun; Hou, Fu-Ju; "3-D Self-Aligned Stacked Ge Nanowires Complementary FET Featuring Single Gate Simple Process," in IEEE Electron Device Letters, vol. 45, no. 10, pp. 2013-2016, Oct. 2024.

  29. Lin, Yi-Wen; Huang, Yu-Hsien; Lin, Shan-Wen; Luo, Guang-Li; Lin, Yu-Hsien; Wu, Yung-Chun; Hou, Fu-Ju; "Self-Induced Ge-Doped HfO2 Applied to Ge Stacked Nanowires Ferroelectric Gate-All-Around Field-Effect Transistor with Steep Subthreshold Slope Under O3 Treatment with GeO2 as Interfacial Layer", ECS Journal of Solid State Science and Technology, 2024.

  30. Chen-You Wei; Yung-Teng Fang; Yi-Ju Yao; Chih-Chao Yang; Fu-Ju Hou; Chien-Chun Chen, "High-Reliability HfO2/ZrO2 Superlattice Ferroelectric Poly-Si FinFET Memory Device Utilizing Green Laser Crystallization," in IEEE Electron Device Letters, 2024.

International Conference

  1. Yung-Chun Wu, Chun-Yen Chang, Ting-Chang Chang, Po-Tsun Liu, Chi-Shen Chen, Chun-HaoTu, Hsiao-Wen Zan, Ya-Hsiang Tai, and Simon Min Sze,“High Performance and High Reliability Polysilicon Thin-Film Transistors with Multiple Nano-Wire Channels,” p. 777-780, 2004 International Electron Device Meeting (IEDM), San Francisco USA.

  2. Yung-Chun Wu, Yuan-Chun Wu, Cheng-Wei Chou, Chun-HaoTu, Jen-Chung Lou, Ting-Chang           Chang, Po-Tsun Liu, and Chun-Yen Chang,“Mobility Enhancement of Pattern-dependent Metal-Induced Lateral Crystallization Polysilicon Thin-Film Transistors with different dimensions,” p. 268-271, 2005 Society for Information Display (SID), Boston, USA.

  3. Yung-Chun Wu, Che-Yu Yang, Chi-Shen Chen, Ting-Chang Chang, Po-Tsun Liu, and Chun-Yen Chang,“The Effects of Electrical Stress and Temperature on the Properties of Polysilicon Thin-Film Transistors with Multiple Nano-Wire Channels,” p. 151-154, 1stInternatioal TFT conference, Seoul, Korea, 2005.

  4. Yung-Chun Wu, Ting-Chang Chang, Cheng-Wei Chou, Yuan-Chun Wu, Chun-HaoTu, Po-Tsun Liu, and Chun-Yen Chang,“High performance Metal-induced Lateral Crystallization Polysilicon Thin-Film         Transistors with Multiple Nano-Wire Channels and Multiple Gates,”The 2005 Silicon Nanoelectronics Workshop (SNW), Kyoto, Japan, 2005.

  5. Yung-Chun Wu, Hung-Bin Chen, Li-Wei Feng, Ting-Chang Chang, Po-Tsun Liu, Chun-Yen Chang,“Reliability Study on Tri-Gate Nanowires Poly-Si TFTs under DC and AC Hot-Carrier Stress,”The 7th IEEE International Conference on Nanotechnology, Hong Kong. 2007

  6. Yung-Chun Wu, Po-Wen Su, Chin-Wei Chang, Min-Feng Hung,“Program/Erase Characteristics of Twin Poly-Si Thin Film Transistors EEPROM withTri-Gate Nanowires structure,”The 2008 Silicon Nanoelectronics Workshop (SNW), Hawaii, USA, 2008.

  7. Lun-Jyun Chen, Yung-Chun Wu*, Ji-Hong Chiang, Chin-Wei Chang, and Po-Wen Su,“Novel Nanowires Ω-Gate Poly-Si TFT Nonvolatile Memory with HfO2 Trapping Layer,”Silicon Nanoelectronics Workshop (SNW), June 13-14, 2009, Kyoto, Japan.

  8. Yung-Chun Wu*, Chien-Ting Chen, Chien-Chun Lin, Guo-chungChi,“Characterization of dye-sensitized solar cells with sputtered various metallic thin films on photoelectrode,”TACT 2009 International Thin Films Conference (TACT 2009). December 14 - 16, 2009,  Taipei, Taiwan.

  9. Yung-Chun Wu*, Ji-Hong Chiang,, Lun-Jyun Chen   *Hung-Bin Chen  Po-Wen Su, Chin-Wei ChangTwin Poly-Si Thin Film Transistors EEPROM withNitride Trapping Layer, International Display Manufacturing Conference & Exhibition (IDMC), April 27-30, 2009, Taipei, Taiwan.

  10. Yung-Chun Wu*, Min-Feng Hung, Ji-Hong Chiang, Jiang-Hung Chen, Lun-Chun Chen,“Fabrication and Characterization of Twin Poly-Si Thin Film Transistors EEPROM with Nitride Trapping Layer,”IEEE International NanoElectronics Conference (INEC)January 3-8, 2010, Hong Kong, China

  11. Min-Feng Hung, Jiang-Hung Chen, and Yung-Chun Wu*,“Pi-Gate Nanowires TANOS Poly-Si TFT Nonvolatile Memory“, Silicon Nanoelectronics Workshop (SNW) June 13-14 2010, Honolulu, USA.

  12. Chao-Kan Yang, Hung-Bin Chen, Ji-Hong Jiang, Yung-Chun Wu*, Chun-Yen Chang,“High Performance Poly-Si Thin-Film Nonvolatile Memory with Dual Gate-All-Around Structure and hybrid trapping layer“, Silicon Nanoelectronics Workshop (SNW) June 13-14 2010, Honolulu, USA.

  13. Yung-Chun Wu*, Min-Feng Hung,  Jiang-Hung Chen, Lun-Chun Chen, and Ji-Hong Jiang,“High-k materials and poly-Si nanowires in nonvolatile memory for 3D flash memory and display panel applications,”Asia-Pacific Workshop on Fundamentals and Applications ofAdvanced Semiconductor Devices, June 30 – July 2, 2010, Tokyo, Japan. (Invited talk).

  14. Yeh Mu Shih, Yung-Chun Wu*, Tang Zih Yun, Hung Min Feng, Lee Yao Jen,“High performance nanoscale n-MOS gate-all-around poly-Si thin film transistors by microwave annealing,” International Conference on Solid State Devices andMaterials (SSDM)Sep. 25 – Sep. 27, 2012, Tokyo, Japan. (Invited talk).

  15. Mu-Shih Yeh*, Kuan-Cheng Liu, Min-Feng Hung, and Yung-Chun Wu*, “High Speed and Good Retention of Ω-Gate P-channel Twin Poly-Si Thin Film Transistors EEPROM,” Silicon Nanoelectronics Workshop (SNW), June 9 – June 10, 2013, Kyoto, Japan.

  16. Yi-RueiJhan, Min-Feng Hung and Yung-Chun Wu*, “Characteristics of Asymmetry-Gate Tunneling Field-Effect Transistor,” Silicon Nanoelectronics Workshop (SNW), June 9 – June 10, 2013, Kyoto, Japan.

  17. Hsin-Yi Lin, Yi-RueiJhan, Min-Feng Hung and Yung-Chun Wu*, “Pi-Gate Tunneling Field-Effect Transistor Charge Trapping Nonvolatile Memory,” Silicon Nanoelectronics Workshop (SNW), June 9 – June 10, 2013, Kyoto, Japan.

  18. Ya-Chi Cheng, Hung-Bin Chen, Ming-Hung Han, Yung-Chun Wu*, Nan-Heng Lu, and Jun-Ji Su, “Characteristics of trapezoidal shaped channel for Junctionless Bulk FinFETs,” Silicon Nanoelectronics Workshop (SNW), June 9 – June 10, 2013, Kyoto, Japan.

  19. Nan-Heng Lu,Yung-Chun Wu*, Hung-Bin Chen, Ya-Chi Cheng, Jun-Ji Su, and Ming-Hung Han, “Temperature Dependence Comparison Between Junctionless and ConventionalPoly-Si Thin-Film Transistor,” Silicon Nanoelectronics Workshop (SNW), June 9 – June 10, 2013, Kyoto, Japan.

  20. Jun-Ji Su, Ya-Chi Cheng, Nan-Heng Lu, Yung-Chun Wu*, and Hung-Bin Chen, “Performance of p-Type Junctionless Poly-Si Thin-Film Transistors with Raised S/D,” Silicon Nanoelectronics Workshop (SNW), June 9 – June 10, 2013, Kyoto, Japan.

  21. Hung-Bin Chen, Yung-Chun Wu*, Chun-Yen Chang, Ming-Hung Han, Nan-Heng Lu, and Ya-Chi Cheng, “Performance of GAA poly-Si Nanosheet (2nm) channel of Junctionless Transistors with ideal Subthreshold Slope,” Symposia on VLSI Technology and circuits (VLSI), June 11 – June 14,2013, Kyoto, Japan. (oral)

  22. Hung-Bin Chen, Yung-Chun Wu* , Chun-Yen Chang, Ming-Hung Han, Nan-Heng Lu, and Ya-Chi Cheng, “Performance of GAA poly-Si Nanosheet (2nm) channel  of Junctionless Transistors with ideal Subthreshold Slope,” VLSI Dig. Tech. 978-4-86348-347-7, 2013.

  23. Ya-Chi Cheng, Hung-Bin Chen, Chi-Shen Shao, Jun-Ji Su, Yung-Chun Wu*,Chun-Yen Chang, and Ting-Chang Chang, “Performance Enhancement of a Novel P-type Junctionless Transistor Using a Hybrid Poly-Si Fin Channel ,”  International          Electron Device Meeting (IEDM), 2014, San Francisco USA.

  24. Mu-Shih Yeh, Yung-Chun Wu* ,Min-Hsin Wu, Yi-RueiJhan, Ming-Hsien Chung, and Min-Feng Hung,“Performance of GAA poly-Si Nanosheet (2nm) channel  of Junctionless Transistors with ideal Subthreshold Slope,” International Electron Device Meeting (IEDM), 2014,San Francisco USA.

  25. Ya-Chi Cheng, Hung-Bin Chen, Chun-Yen Chang, Life Fellow, IEEE , Yi-Jia Shih, and Yung-Chun Wu, Member, IEEE ,“A Highly Scalable Poly-Si Junctionless FETs Featuring a Novel Multi-Stacking Hybrid PN Layer and Vertical Gate for 3D Stacked ICs ”, Symposia on VLSI Technology and circuits (VLSI) Hilton Hawaiian Village,  Honolulu, HI, accepted to publish, 2016.

  26. Y.-W. Lin, T.-Y. Yu, C.-J. Su, Y.-N. Chen, H.-H. Chang, G.-L. Luo, C.-T. Wu, W.-F. Wu, K.-L. Lin, F.-J. Hou,*, Y.-C. Wu, and W.-K. Yeh, "Sub-60 mV/dec Germanium Nanowire Field-Effect Transistors with 2-nm-thick Ferroelectric Hf0.5Zr0.5O2," 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2021, pp. 1-2, doi: 10.1109/VLSI-TSA51926.2021.9440120.

  27. Y.-W. Lin, T.-Y. Yu, C.-J. Su, Y.-N. Chen, H.-H. Chang, G.-L. Luo, C.-T. Wu, W.-F. Wu, K.-L. Lin, F.-J. Hou*, Yung-Chun Wu*, and W.-K. Yeh, “Sub-60 mV/dec Germanium Nanowire Field-Effect Transistors with 2-nm-thick Ferroelectric Hf0.5Zr0.5O2”, 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2021, pp. 1-2, Hsinchu, Taiwan. 

  28. Chih-Hsiang Chang, Siao-Cheng Yan, Chong-Jhe Sun, Ming-Yueh Huang, Bo-An Chen, Xin-Chan Zhong, Yi-Wen Lin, Yung-Chun Wu*, “Green Laser Crystallized Poly-Si Thin-film Transistor and CMOS Inverter using HfO2-ZrO2 Superlattice Gate Insulator and Microwave Annealing for BEOL Applications”, Silicon Nanoelectronics Workshop (SNW), 2023, Kyoto, Japan.

  29. Xin-Chan Zhong, Siao-Cheng Yan, Ming-Yueh Huang, Chih-Siang Chang, Chong-Jhe Sun, Bo-An Chen, Yi-Wen Lin, Yung-Chun Wu*, “Study of Ferroelectric HfO2-ZrO2 Superlattice Poly-Si Junctionless Nanosheet Gate-all-around Field-effect-transistor and CMOS Inverter Superlattice Gate Insulator and Microwave Annealing for BEOL Applications”, Silicon Nanoelectronics Workshop (SNW), 2023, Kyoto, Japan.

  30. Ming-Yueh Huang, Siao-Cheng Yan, Xin-Chan Zhong, Chih-Siang Chang, Chong-Jhe Sun, Bo-An Chen, Yi-Wen Lin, Yung-Chun Wu*, “Investigation of HfO2/ZrO2 Superlattice Dielectric and High-k AlON Interfacial Layer on Ferroelectric FinFET”, Silicon Nanoelectronics Workshop (SNW), 2023, Kyoto, Japan.

  31. Bo-An Chen, Yi-Wen Lin, Hao-Hsiang Chang, Chih-Hsiang Chang, Ming-Yueh Huang, Xin-Chan Zhong, Siao-Cheng Yan, Chong-Jhe Sun, Fu-Ju Hou, Yung-Chun Wu*, “Vertically Stacked Ge Diamond-shape Nanowires GAAFET with Ferroelectric HZO”, Silicon Nanoelectronics Workshop (SNW), 2023, Kyoto, Japan.

  32. ​Chang, Chih-Hsiang; Yan, Siao-Cheng; Sun, Chong-Jhe; Huang, Ming-Yueh; Chen, Bo-An; Zhong, Xin-Chan; Lin, Yi-Wen; Wu, Yung-Chun; "Green Laser Crystallized Poly-Si Thin-film Transistor and CMOS Inverter using Hfo2-Zro2 Superlattice Gate Insulator and Microwave Annealing for BEOL Applications," 2023 Silicon Nanoelectronics Workshop (SNW), Kyoto, Japan, 2023.

  33. Huang, Ming-Yueh; Yan, Siao-Cheng; Zhong, Xin-Chan; Chang, Chih-Siang; Sun, Chong-Jhe; Chen, Bo-An; Lin, Yi-Wen; Wu, Yung-Chun; "Investigation of HfO2/ZrO2 Superlattice Dielectric and High-k AION Interfacial Layer on Ferroelectric FinFET," 2023 Silicon Nanoelectronics Workshop (SNW), Kyoto, Japan, 2023.

  34. Zhong, Xin-Chan; Yan, Siao-Cheng; Huang, Ming-Yueh; Chang, Chih-Siang; Sun, Chong-Jhe; Chen, Bo-An; Lin, Yi-Wen; Wu, Yung-Chun; "Study of Ferroelectric HfO2-ZrO2 Superlattice Poly-Si Junctionless Nanosheet Gate-all-around Field-effect-transistor and CMOS Inverter," 2023 Silicon Nanoelectronics Workshop (SNW), Kyoto, Japan, 2023.

專利

美國發明專利

貴方卷號：K3P108030-US

聖島編號：NPE-26872-AM

申 請 人：國立清華大學

發 明 人：吳永俊、侯福居、蔡孟儒

案件名稱：具超薄結晶性氧化鉿鋯之閘極介電層的鐵電電晶體裝置FERROELECTRIC FIELD EFFECT TRANSISTOR 

                  DEVICE

申 請 日：2020/6/30

申 請 號：16/917172

公 開 日：2021/1/28

公 開 號：US2021/0028292A1

 

清大編號    持續維護(Y/N)     放棄原因    系所  學院  申請人        發明人        國別  專利類別    專利名稱    年費有效期限

1. K3P102037-TW         工程與系統科學系        原子科學院          吳永俊        陳弘斌  韓銘鴻

吳永俊        中華民國    發明  具反極性結構的無接面電晶體        2019-04-20

2. K3P102079-US          工程與系統科學系        原子科學院          吳永俊        詹易叡

吳永俊        美國  發明  非對稱閘極的穿隧式電晶體            2019-01-07

台積電合作申請的「乾式蝕刻(Dry-etch)形成溝槽式(Trench)超薄主動層(UTB)無接面式電晶體(JL FinFET)」 (計畫參與學生:賴政杰、陳光鑫、葉沐詩)

 

  1. 專利編號200612560，薄膜電晶體及其製造方法 THIN FILM TRANSISTOR AND FABRICATING METHOD THEREOF，張鼎張 TING-CHANG CHANG ;吳永俊 YUNG-CHUN WU ;劉柏村 PO-TSUN LIU ;張俊彥 CHUN-YEN CHANG，公開日期2006/04/16。

  2. 專利編號200622243，奈米生化感測元件及其製造方法 NANO-BIOCHEMICAL SENSOR AND ABRICATING METHOD THEREOF，張鼎張 CHANG, TING-CHANG ;王敏全 WANG, MING-CHAUNG ;劉柏村 LIU, PO-TSUN ;吳永俊 WU, YUNG-CHUN ;陳紀文 CHEN, CHI-WEN ;戴亞翔 TAI, YA-HSIANG，公開日期 2006/07/01。

  3. 專利編號200701313，多晶矽薄膜電晶體及其製造方法 POLYSILICON THIN-FILM TRANSISTORS AND FABRICATING METHOD THEREOF，張鼎張 TING-CHANG CHANG ;劉柏村 PO-TSUN LIU ;吳永俊 YUNG-CHUN WU，公開日期 2007/01/01。

  4. 專利編號200810116，具非揮發性記憶功能之薄膜電晶體裝置 THIN FILM TRANSISTOR DEVICE WITH NONVOLATILE MEMORY FUNCTION，張鼎張 CHANG, TING CHANG ;陳世青 CHEN, SHIH CHING ;劉柏村 LIU, PO TSUN ;吳永俊 WU, YUNG CHUN，公開日期 2008/02/16。

  5. 專利編號421639，一種沈積奈米級金粒子的方法，胡淑芬 ;葉儒林 ;劉如熹 ;吳永俊 ;黃調元，公開日期 2001/02/11。

  6. 專利編號550797，自我對準之複晶矽間隙壁閘極之單電子電晶體結構及其製造方法，胡淑芬 ;吳永俊 ;盧文泰 ;劉學欣 ;黃調元 ;趙天生，公開日期 2003/09/01。

  7. 專利編號I279840，多晶矽薄膜電晶體及其製造方法 POLYSILICON THIN-FILM TRANSISTORS AND FABRICATING METHOD THEREOF，張鼎張 CHANG, TING CHANG ;劉柏村 LIU, PO TSUN ;吳永俊 WU, YUNG CHUN，公開日期 2007/04/21。

  8. 專利編號I293685，奈米生化感測元件及其製造方法 NANO-BIOCHEMICAL SENSOR AND FABRICATING METHOD THEREOF，張鼎張 CHANG, TING CHANG ;王敏全 WANG, MING CHAUNG ;劉柏村 LIU, PO TSUN ;吳永俊 WU, YUNG CHUN ;陳紀文 CHEN, CHI WEN ;戴亞翔 TAI, YA HSIANG，公開日期 2008/02/21。

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奈米綠能電子元件實驗室   國立清華大學 工程與系統科學系


Nanoelectronic X-FET Green Devices Labortory       

National Tsing Hya University, Department of Engineering and System Science

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